A digital CMOS design technique for SEU hardening

IEEE Transactions on Nuclear Science

Volumn 47, Issue 6 III, 2000, Pages 2603-2608

  Baze, Mark P ^a   Buchner, Steven P ^b   McMorrow, Dale ^c  

^a BOEING COMPANY   (United States)

^b SFA INC   (United States)

^c NAVAL RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DATA STORAGE EQUIPMENT; DIGITAL INTEGRATED CIRCUITS; HARDENING; LOGIC DESIGN; TRANSIENTS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

LOGIC CELL; SINGLE EVENT UPSET;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034451186     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.903815     Document Type: Conference Paper

References (12)

1. An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM
2. An SEU-hardened CMOS latch design
3. SEU hardened memory cells for a CCDS Reed Solomon encoder
4. SEU-hardened resistive-load static RAM's
5. SEU simulation and testing of resistor-hardened d-latches in the SA3300 microprocessor
6. Design of SEU hardened memorycells: The hit cell
7. Low power SEU immune CMOS memory circuits
8. Test results for SEU and SEL immune memory circuits
9. Application of pulsed laser for evaluation and optimization of SEU-hard designs
10. Critical evaluation of the pulsed laser method for single-event effects testing and fundamental studies
11. Pulsed laser-induced SEU in integrated circuits: A practical method for hardness assurance testing
12. SEU tolerant locally-clocked dynamic logic