Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications

Microelectronic Engineering

Volumn 84, Issue 9-10, 2007, Pages 2398-2403

  Asenov, A ^a   Kalna, K ^a   Thayne, I ^a   Hill, R J W ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

CMOS; High gate dielectric; Implant free III V MOSFETs; Monte Carlo simulations

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIELECTRIC DEVICES; HETEROJUNCTIONS; INFORMATION MANAGEMENT; MONTE CARLO METHODS; OHMIC CONTACTS; THRESHOLD VOLTAGE; TRANSISTORS;

GATE DIELECTRIC; IMPLANT FREE III-V MOSFETS; METAL GATE;

MOSFET DEVICES;

EID: 34249103333     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.04.117     Document Type: Article

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