Concurrent HCI-NBTI: worst case degradation condition for 65 nm p-channel SOI MOSFETs

Microelectronic Engineering

Volumn 84, Issue 9-10, 2007, Pages 2085-2088

  Mishra, R ^a   Mitra, S ^b   Gauthier, R ^b   Ioannou, D E ^a   Seguin, C ^b   Halbach, R ^b  

^a Krasnow Institute for Advanced Study   (United States)

^b IBM   (United States)

Author keywords

Concurrent HCI NBTI; HCI; NBTI; SOI

Indexed keywords

CIRCUIT SIMULATION; ELECTRIC POTENTIAL; SILICON ON INSULATOR TECHNOLOGY;

BODY BIAS; BODY CONTACTED (BC) DEVICES; STRESS VOLTAGES;

MOSFET DEVICES;

EID: 34248679330     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.04.016     Document Type: Article

References (9)

1. Koyanagi M., Lewis A.G., Martin R.A., Huang T.Y., and Chen J.Y. Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's. IEEE-TED 34 (1987) 839-844
2. Tsuchiya T., Okazaki Y., Miyake M., and Kobayashi T. New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET. IEEE TED 39 (1992) 404-408
3. Woltjer R., Paulzen G.M., Pomp H.G., Lifka H., and Woerlee P.H. Three hot-carrier degradation mechanism in deep-submicron PMOSFETs. IEEE TED 42 (1995) 109-115
4. Ioannou D.E., Duan F.L., Sinha S.P., and Zaleski A. Opposite-channel-based injection of hot-carriers in SOI MOSFET's: Physics and Applications. IEEE TED 45 (1998) 1147-1154
5. Ioannou D.P., Mishra R., Ioannou D.E., Liu S.T., and Hughes H.L. Worst case stress conditions for hot carrier induced degradation of p-channel SOI MOSFETs. Solid State Electronics 50 (2006) 929-934
6. Schroder D.K., and Babcock J.A. Negative bias temperature instability: road to cross in deep submicron semiconductor manufacturing. J. Appl. Phys. 94 (2003) 1-18
7. E. Leobandung et al, High performance 65nm SOI technology with dual stress liner and low capacitance SRAM cell, VLSI Symp.(2005) 126-127.
8. Yeh W.K., Wang W.H., Fang Y.K., Chen M.C., and Yang F.L. Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 μm CMOSFET with 2-nm thin gate oxide. IEEE TED 49 (2002) 2157-2162
9. G. La Rosa, F. Gaurin, S. Rauch, A. Acovic, J. Lukaitis, E. Crabbe, NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies, IEEE Int. Rel. Phy. Sym. (1997) 282-286.