A 4-kB 500-MHz 4-T CMOS SRAM using LOW-VTHN bitline drivers and high-VTHP latches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 9, 2004, Pages 901-909

  Wang, Chua Chin ^a   Tseng, Yih Long ^a   Leo, Hon Yuan ^b   Hu, Ron ^c  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b HIMAX TECHNOLOGIES INC   (Taiwan)

^c Asuka Semiconductor Inc   (Taiwan)

Author keywords

4 T SRAM; ATD; Dual threshold; SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA HANDLING; LEAKAGE CURRENTS; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE; VOLTAGE REGULATORS;

4-T SRAM; ATD; DUAL THRESHOLD VOLTAGE TRANSISTORS; WORDLINE VOLTAGE COMPENSATION (WLC);

STATIC RANDOM ACCESS STORAGE;

EID: 4544296978     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.833669     Document Type: Article

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