Microprocessor verification via feedback-adjusted Markov models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 6, 2007, Pages 1126-1138

  Wagner, Ilya ^a,b   Bertacco, Valeria ^a,b   Austin, Todd ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Architectural simulation; Directed random simulation; High performance simulation

Indexed keywords

ARCHITECTURAL SIMULATION; DIRECTED RANDOM SIMULATION; HIGH PERFORMANCE SIMULATION;

CLOSED LOOP CONTROL SYSTEMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ERROR ANALYSIS; MARKOV PROCESSES;

MICROPROCESSOR CHIPS;

EID: 34247629721     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.884494     Document Type: Article

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