Overlay as the key to drive wafer scale 3D integration

Microelectronic Engineering

Volumn 84, Issue 5-8, 2007, Pages 1412-1415

  Steen, Steven E ^a   LaTulipe, Douglas ^a   Topol, Anna W ^a   Frank, David J ^a   Belote, Kevin ^b   Posillico, Dominick ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

3D integration; 3DIC; Alignment; Oxide fusion bonding; Wafer bonding

Indexed keywords

FILM GROWTH; INTEGRATED CIRCUITS; LITHOGRAPHY; SILICON; THREE DIMENSIONAL; WAFER BONDING;

3D INTEGRATION; ALIGNMENT ACCURACY; OXIDE FUSION BONDING; STACKING;

WSI CIRCUITS;

EID: 34247570463     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.01.231     Document Type: Article

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