New Buried Bit-line NAND (BiNAND) Flash Memory for Data Storage

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 95-96

  Chang, Sean ^a   Yang, Evans ^b   Chen, Terry ^a   Huang, Lizzy ^a   Hsu, Bennett ^a   Sung, Da ^c   Duh, Jiang Chi ^c   Hung, Chi Wei ^c   Huang, Vincent ^c   King, Ya Ching ^b   Chu, Chih Hsiun ^a   Hsu, Charles Ching Hsiang ^a  

^a EMEMORY TECHNOLOGY INC   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c POWERCHIP TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC CONDUCTIVITY; ELECTRIC POTENTIAL; FLASH MEMORY; MEMORY ARCHITECTURE; NAND CIRCUITS;

GATE VOLTAGE;

FLASH MEMORY; THRESHOLD VOLTAGE;

BIT LINES; BIT-LINE ANDS; DATA STORAGE; ERASE VOLTAGES; LOW VOLTAGES; MULTILEVELS; NAND FLASH; NAND FLASH MEMORY; PROGRAM/ERASE; VOLTAGE PROGRAMMING;

EID: 0141761535     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J.-D. Choi et al, in IEDM Tech. Dig., 2001, pp. 25-28.
2. S. Satoh et al, in IEDM Tech. Dig., 1997, pp. 291-294.
3. H. S. Kim et al, in VLSI Tech. Dig., 1997, pp. 65-66.