Selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 166-167

  Kurata, Hideaki ^a   Kobayashi, Naoki ^a   Kimura, Katsutaka ^a   Saeki, Shunichi ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; MOSFET DEVICES;

FLASH MEMORIES; HIGH-SPEED PROGRAMMING; MULTILEVEL PROGRAMMING;

DATA STORAGE EQUIPMENT;

EID: 0033698081     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)