Power modeling and efficient FPGA implementation of FHT for signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 3, 2007, Pages 286-295

  Amira, Abbes ^a,b   Chandrasekaran, Shrutisagar ^a,b  

^a IEEE   (United Kingdom)

^b BRUNEL UNIVERSITY   (United Kingdom)

Author keywords

Discrete orthogonal transforms (DOTs); Distributed arithmetic; Fast Hadamard transform (FHT); Field programmable gate array (FPGA); Power modeling; Sparse matrices

Indexed keywords

DISCRETE ORTHOGONAL TRANSFORMS (DOT); DISTRIBUTED ARITHMETICS; FAST HADAMARD TRANSFORM (FHT); POWER MODELING; SPARSE MATRICES;

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE ANALYSIS; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; SIGNAL PROCESSING;

VLSI CIRCUITS;

EID: 34247121470     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893606     Document Type: Article

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