Accelerating colour space conversion on reconfigurable hardware

Image and Vision Computing

Volumn 23, Issue 11, 2005, Pages 935-942

  Bensaali, F ^a   Amira, A ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Colour space conversion; Distributed arithmetic; Field programmable gate array

Indexed keywords

COMPUTER HARDWARE; DATA REDUCTION; DECODING; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE COMPRESSION; OPTIMIZATION; VIDEO SIGNAL PROCESSING;

COLOR SPACE CONVERSION; DECODERS; DISTRIBUTED ARITHMETIC (DA); PROCESSING POWER;

IMAGE PROCESSING;

EID: 25144513063     PISSN: 02628856     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.imavis.2005.03.006     Document Type: Article

References (23)

1. B. Payette, Color space converter: R′G′B′ to Y′CrCb, Xilinx Aplication Note, XAPP637, V1.0, September, 2002.
2. C. Poynton A Technical Introduction to Digital Video 1996 Wiley New York
3. R.C. Gonzalez, and R.E. Woods Digital Image Processing second ed. 2002 Prentice-Hall Englewood Cliffs, NJ
4. Data sheet (www.amphion.com ), Color Space Converters, Amphion semiconductor Ltd, DS6400 V1.1, April, 2002.
5. Application Note (www.cast-inc.com ), CSC Color Space Converter, CAST Inc., April, 2002.
6. Datasheet (www.alma-tech.com ), High Performance Color Space Converter, ALMA Technologies, May 2002.
7. M. Sima, S. Vassiliadis, S.D. Cotofana, and J.T.J. van Eijndhoven Color space conversion for MPEG decoding on FPGA-augmented TriMedia processor The 14th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP'03), Netherlands, June 2003 pp. 250-259
8. F. Bensaali, A. Amira, Design and efficient FPGA implementation of an RGB to YCrCb color space converter using distributed arithmetic, Proceedings of the International Conference on Field Programmable Logic (FPL), Lecture Notes in Computer Science, to be published by Springer, August, 2004.
9. A. Amira, A Custom Coprocessor for Matrix Algorithm, PhD thesis, Queen's University of Belfast, 2001.
10. F. Bensaali, A. Amira, I.S. Uzun, and A. Ahmedsaid An FPGA implementation of 3D affine transformations The 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS'03), Sharjah, UAE, December 2003
11. F. Bensaali, A. Amira, I.S. Uzun, and A. Ahmedsaid Efficient implementation of large parallel matrix product for DOTs The International Conference on Computer, Communication and Control Technologies (CCCT'03), Florida, USA, July 2003
12. Datasheet, (www.celoxica.com ), RC1000 Reconfigurable hardware development platform, Celocixa Ltd, 2001.
13. URL: www.xilinx.com.
14. A. Albiol, L. Torres, and E.J. Delp An unsupervised color image segmentation algorithm for face detection applications Proceedings of the International Conference on Image Processing, October vol. 2 2001 pp. 681-684
15. P. Kuchi, P. Gabbur, P.S. Bhat, and S. David Human face detection and tracking using skin color modelling and connected component operators The IETE Journal of Research, Special issue on Visual Media Processing May 2002
16. M. Bartkowiak Optimisations of color transformation for real time video decoding Digital Signal Processing for Multimedia Communications and Services, EURASIP ECMCS 2001, Budapest, September 2001
17. J.L. Mitchell, and W.B. Pennebaker MPEG Video Compression Standard 1996 Chapman and Hall London
18. J. Bracamonte, P. Standelmann, M. Ansorge, and F. Pellandini A multiplierless implementation scheme for the JPEG image coding algorithm IEEE Nordic Signal Processing Symposium, Kolmarden, Sweden, June 13-15 2000
19. A. Amira An FPGA based parameterisable system for discrete Hartley transforms implementation Proceedings of the International Conference on Image Processing (ICIP), Barcelona, Spain, September 2003
20. H. Ohlsson, and L. Wanhammer Maximally fast numerically equivalent state-space recursive digital filters using distributed arithmetic Proceedings of the IEEE Symposium in Nordic Signal Processing (NORSIG2000), Kolmarden, Sweden, June 2000 pp. 295-298
21. O. Gustafsson, and L. Wanhammar Implementation of a digital beamformer in an FPGA using distributed arithmetic Proceedings of the IEEE Symposium in Nordic Signal Processing (NORSIG2000) Kolmarden, Sweden, June 2000 pp. 295-298
22. Application Note, Xilinx CoreGen, Handel-C, AN 58 v1.0, 2001.
23. Manual, (www.celoxica.com ) Handel-C Language Reference Manual, Celocixa Ltd, 2003.