Novel FPGA implementations of Walsh-Hadamard transforms for signal processing

IEE Proceedings: Vision, Image and Signal Processing

Volumn 148, Issue 6, 2001, Pages 377-383

  Amira, A ^a   Bouridane, A ^a   Milligan, P ^a   Roula, M ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; GRAPHICAL USER INTERFACES; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; ROM; SPEECH CODING;

FAST HADAMARD TRANSFORM (FHT); SPEECH COMPRESSION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035717395     PISSN: 1350245X     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-vis:20010674     Document Type: Conference Paper

References (12)

1. Family of unified complex Hadamard transforms
2. RCMAT: A reconfigurable coprocessor for matrix algorithms
3. High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier
4. A bit level systolic army for Walsh-Hadamard transforms
5. Hadamard transforms on multiply/add architecture
6. New distributed arithmetic algorithm and its application to IDCT
7. A modular approach to the computation of convolution sum using distributed arithmetic principles
8. A novel architecture for Walsh-Hadamard transforms using distributed arithmetic principles
9. A high throughput, FPGA implementation of a bit-level matrix product