Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures

IEE Proceedings: Computers and Digital Techniques

Volumn 149, Issue 1, 2002, Pages 17-24

  Amira, A ^a   Bouridane, A ^a   Milligan, P ^a   Belatreche, A ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COSINE TRANSFORMS; DISCRETE FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; LOGIC DESIGN; MATHEMATICAL MODELS; MATRIX ALGEBRA; SIGNAL PROCESSING; VECTORS;

BAUGH-WOOLEY ALGORITHM; BIT LEVEL SYSTOLIC STRUCTURES; DISCRETE ORTHOGONAL TRANSFORMS; MATRIX-MATRIX MULTIPLICATION; VECTOR MULTIPLICATION;

SYSTOLIC ARRAYS;

EID: 0036187481     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20020159     Document Type: Article

References (19)

1. A high throughput FPGA implementation of a bit-level matrix product
2. Mapping full-systolic arrays for matrix product on Xilinx's XC4000
3. The use of data dependence graphs in the design of bit-level systolic arrays
4. High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier
5. A two's complement parallel array multiplication algorithm
6. Some new designs of 2-D array for matrix multiplication and transitive closure
7. Design of efficient regular arrays for matrix multiplication by two-step regularization
8. A comparison of FPGA implementation of two's complement bit-level and word-level matrix multiplier
9. A VLSI chip for the winograd/prime-factor algorithm to compute the discrete fourier transform
10. Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime-factor decomposition
11. RCMAT: A reconfigurable coprocessor for matrix algorithms
12. VLSI implementation of a 16 × 16 discrete cosine transform
13. Novel VLSI implementation of (8 × 8) point 2-D DCT
14. A novel architecture for Walsh Hadamard transforms using distributed arithmetic principles
15. A re-evaluation of the practicality of floating-point operation on FPGA's