Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment)

IET Information Security

Volumn 1, Issue 1, 2007, Pages 1-10

  Good, T ^a   Benaissa, M ^a  

^a UNIVERSITY OF SHEFFIELD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); DATA TRANSFER; FEEDBACK; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC DESIGN; SERVERS;

ADVANCED ENCRYPTION STANDARD (AES); DECIPHERS; ENCIPHERS;

CRYPTOGRAPHY;

EID: 34047230768     PISSN: 17518709     EISSN: 17518717     Source Type: Journal    
DOI: 10.1049/iet-ifs:20060059     Document Type: Article

References (17)

1. National Institute of Standards and Technology (NIST): ' Advanced Encryption Standard (AES) ', 197, November, 2001, Federal Information Processing Standards (FIPS) Publication
2. Hodjat, A., and Verbauwhede, I.: ' A 21.54Gbits/s fully pipelined AES processor on FPGA ', Proc. 12th Annual IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM'04), April, 2004, Napa, CA, USA, p. 308-309
3. Zambreno, J., Nguyen, D., and Choudhary, A.: ' Exploring area/delay tradeoffs in an AES FPGA implementation ', FPL 2004, 2004, Antwerp, Belgium, p. 575-585, (Lect. Notes Comput. Sci., 3203)
4. Zhang, X., and Parhi, K.K.: ' High-speed VLSI architectures for the AES algorithm ', IEEE Trans. VLSI Syst., 2004, 12, (9), p. 957-967 10.1109/TVLSI.2004.832943 1063-8210
5. Rudra, A., Dubey, P.K., Jutla, C.S., Kumar, V., Rao, J.R., and Rohatgi, P.: ' Efficient implementation of Rijndael encryption with composite field arithmetic ', CHES 2001, May, 2001, Paris, France, p. 171-184, (Lect. Notes Comput. Sci., 2162)
6. Jarvinen, K.U., Tommiska, M.T., and Skytta, J.O.: ' A fully pipelined memoryless 17.8Gbps AES-128 encryptor ', Proc. Int. Symp. Field-Programmable Gate Arrays (FPGA 2003), February, 2003, Monterey, CA, USA, p. 207-215
7. Saggese, G.P., Mazzeo, A., Mazocca, N., and Strollo, A.G.M.: ' An FPGA based performance analysis of the unrolling, tiling and pipelining of the AES algorithm ', FPL 2003, September, 2003, Lisbon, Portugal, p. 292-302, (Lect. Notes Comput. Sci., 2778)
8. Standaert, F., Rouvroy, G., Quisquater, J., and Legat, J.: ' Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs ', CHES 2003, September, 2003, Cologne, Germany, p. 334-350, (Lect. Notes Comput. Sci., 2779)
9. Rijmen, V.: ' Efficient implementation of the Rijndael S-box ', http://www.iaik.tu-graz.ac.at/research/krypto/AES/old/∼rijmen/rijndael/sbox. pdf
10. Wolkerstorfer, J., Oswald, E., and Lamberger, M.: ' An ASIC implementation of the AES SBoxes ', CT-RSA 2002, February, 2002, San Jose, CA, USA, p. 67-78, (Lect. Notes Comput. Sci., 2271)
11. Paar, C.: ' Efficient VLSI architectures for bit-parallel computation in Galois fields ', June, 1994, PhD, Institute for Experimental Mathematics, University of Essen, Essen, Germany
12. Satoh, A., Morioka, S., Takano, K., and Munetoh, S.: ' A compact Rijndael hardware architecture with S-Box optimization ', ASIACRYPT 2001, December, 2001, Gold Coast, Australia, p. 239-254, (Lect. Notes Comput. Sci., 2248)
13. Good, T., and Benaissa, M.: ' AES from the fastest to the smallest ', CHES 2005, September, 2005, Edinburgh, Scotland, p. 427-440, (Lect. Notes Comput. Sci., 3659)
14. Daemen, J., and Rijmen, V.: ' AES proposal: Rijndael ', 1999, version 2, March), http://www.nist.gov/aes
15. 8) ', Proc. ENZCon'03, September, 2003, University of Waikato, New Zealand
16. Mastrovito, E.: ' VLSI architectures for compositions in Galois fields ', 1991, PhD, Linkoping University, Linkoping, Sweden
17. m) ', Trans. IEICE, 1989, E72, (1), p. 37-42