Functional test generation using property decompositions for validation of pipelined processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Koo, Heon Mo ^a   Mishra, Prabhat ^a  

^a UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRONIC EQUIPMENT TESTING; LOGIC DESIGN; MODEL CHECKING;

PROCESSOR DESIGN; PROCESSOR VALIDATION;

PROGRAM PROCESSORS;

EID: 34047194779     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. A. Adir et al. Genesys-pro: Innovations in test program generation for functional processor verification. Design & Test, 2004.
2. A. Aharon et al. Test program generation for functional verification of PowerPC processors in IBM. DAC, 1995.
3. A. Halambi et al. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. DATE, 1999.
4. C. Jacobi. Formal verification of complex out-of-order pipelines by combining model-checking and theorem-proving. CAV, 2002.
5. D. Campenhout et al. High-level test generation for design verification of pipelined microprocessors. DAC, 1999.
6. E. Clarke, O. Grumberg and D. Peled. Model Checking. MIT Press, Cambridge, MA, 1999.
7. E. Clarke et al. Efficient generation of counterexamples and witnesses in symbolic model checking. DAC, 1995.
8. G. Parthasarathy et al. Safety property verification using sequential SAT and bounded model checking. Design & Test, 2004.
9. H. Iwashita et al. Automatic test pattern generation for pipelined processors. ICCAD, 580-583, 1994.
10. www-cad.eecs.berkeley.edu/~kenmcmil/smv. Cadence SMV.
11. I. Wagner, V. Bertacco and T. Austin. Stresstest: An automatic approach to test generation via activity monitors. DAC, 2005.
12. J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2003.
13. M. Behm et al. Industrial experience with test generation languages for processor verification. DAC, 36-40, 2004.
14. P. Bjesse and J. Kukula. Using counter example guided abstraction refinement to find complex bugs. DATE, 2004.
15. P. Ho and A. Isles and T. Kam. Formal verification of pipeline control using controlled token nets and abstract interpretation. ICCAD, 529-536, 1998.
16. P. Mishra and N. Dutt. Graph-based functional test program generation for pipelined processors. DATE, 182-187, 2004.
17. P. Mishra and N. Dutt. Functional Verification of Programmable Embedded Architectures - A Top-Down Approach. Springer, 2005.
18. R. Ho et al. Architecture validation for processors. ISCA, 1995.
19. R. Jhala and K. L. McMillan. Microarchitecture verification by compositional model checking. CAV, 2001.
20. S. Fine and A. Ziv. Coverage directed test generation for functional verification using bayesian networks. DAC, 286-291, 2003.
21. S. Ur and Y. Yadin. Micro architecture coverage directed generation of test programs. DAC, 175-180, 1999.