Test program generation for functional verification of PowerPC processors in IBM

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 279-285

  Aharon, Aharon, ^a   Goodman, Dave ^a   Levinger, Moshe ^a   Lichtenstein, Yossi ^a   Malka, Yossi ^a   Metzger, Charlotte ^a   Molcho, Moshe ^a   Shurek, Gil ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; COMPUTER TESTING; DATA ACQUISITION; DATABASE SYSTEMS; HEURISTIC PROGRAMMING; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON;

FUNCTIONAL VERIFICATION; HEURISTIC DATABASE; POWERPC PROCESSORS; TEST PROGRAM GENERATION;

EXPERT SYSTEMS;

EID: 0029230835     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217542     Document Type: Conference Paper

References (6)