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Volumn 2, Issue , 2006, Pages

A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs

Author keywords

[No Author keywords available]

Indexed keywords

MIXED MODE DELAY LOCKED LOOP (MMDLL); MULTIPHASE OUTPUTS; TIME TO DIGITAL CONVERTERS (TDC); VOLTAGE CONTROLLED DELAY LINE (VCDL);

EID: 34047184300     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269064     Document Type: Conference Paper
Times cited : (4)

References (8)
  • 1
    • 0035333219 scopus 로고    scopus 로고
    • A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines
    • May
    • Y. J. Jung et al., "A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines," IEEE J. Solid-State Circuits, vol.36, no.5, pp. 784-791, May. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.5 , pp. 784-791
    • Jung, Y.J.1
  • 2
    • 0035273837 scopus 로고    scopus 로고
    • CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator
    • Mar
    • D. J. Foley et al., "CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE J. Solid-State Circuits, vol.36, no.3, pp. 417-423, Mar. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.3 , pp. 417-423
    • Foley, D.J.1
  • 3
    • 0033894074 scopus 로고    scopus 로고
    • An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance
    • Mar
    • Y. Moon et al., "An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance," IEEE J. Solid-State Circuits, vol.35, no.3, pp. 377-384, Mar. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.3 , pp. 377-384
    • Moon, Y.1
  • 4
    • 0032635505 scopus 로고    scopus 로고
    • A Portable Digital DLL for High-speed CMOS Interface Circuits
    • May
    • B.W. Garlepp et al., "A Portable Digital DLL for High-speed CMOS Interface Circuits," IEEE J. Solid-State Circuits, vol.34, no.5, pp. 632-644, May. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.5 , pp. 632-644
    • Garlepp, B.W.1
  • 5
    • 0036684711 scopus 로고    scopus 로고
    • A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle
    • Aug
    • H. H. Chang et al., " A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle," IEEE J. Solid-State Circuits, vol.37, no.8, pp. 1021-1027, Aug. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.8 , pp. 1021-1027
    • Chang, H.H.1
  • 6
    • 0031276490 scopus 로고    scopus 로고
    • A Semidigital Dual Delay-Locked Loop
    • Nov
    • S. Sidiropoulos et al., "A Semidigital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol.32, no.11, pp. 1683-1692, Nov. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.11 , pp. 1683-1692
    • Sidiropoulos, S.1
  • 7
    • 0036612252 scopus 로고    scopus 로고
    • A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM
    • June
    • S. J. Kim et al., "A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM," IEEE J. Solid-State Circuits, vol.37, no.6, pp. 726-734, June. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.6 , pp. 726-734
    • Kim, S.J.1
  • 8
    • 0030290680 scopus 로고    scopus 로고
    • Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques
    • Nov
    • J. G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1723-1732
    • Maneatis, J.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.