Self-aligned wafer-level integration technology with high-density interconnects and embedded passives

IEEE Transactions on Advanced Packaging

Volumn 30, Issue 1, 2007, Pages 11-18

  Sharifi, Hasan ^a   Choi, Tae Young ^b   Mohammadi, Saeed ^a  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Heterogeneous integration; Packaging; System on chip (SOC); System on package (SIP); Wafer scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; FABRICATION; INTEGRATED CIRCUIT MANUFACTURE; SUBSTRATES; WSI CIRCUITS;

DIE-TO-DIE INTERCONNECTS; HETEROGENEOUS INTEGRATION; SYSTEM-ON-CHIP (SOC); SYSTEM-ON-PACKAGE (SIP);

CHIP SCALE PACKAGES;

EID: 33947408372     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2006.890221     Document Type: Article

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