IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 18-25

  Lu, Meng ^a   Savaria, Yvon ^b   Qiu, Bing ^a   Taillefer, Jacques ^a  

^a INSTITUTE FOR RESEARCH IN IMMUNOLOGY AND CANCER   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHAINS; DEFECTS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; RECONFIGURABLE HARDWARE; WSI CIRCUITS;

CONTROL SIGNAL; FAULT-TOLERANT; IEEE 1149.1; INTEGRATED SYSTEMS; LAYOUT REGULARITY; SENSITIVE CIRCUITS; TRIPLE MODULAR REDUNDANCY; YIELD ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 84971322282     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250091     Document Type: Conference Paper

References (13)

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