Evolution of substrate noise generation mechanisms with CMOS technology scaling

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 2, 2006, Pages 296-305

  Badaroglu, Mustafa ^a,b   Wambacq, Piet ^a,b,c   Van Der Plas, Geert ^a,b   Donnay, Stéphane ^a,b   Gielen, Georges G E ^a,d   De Man, Hugo J ^a,b,d  

^a IEEE   (Belgium)

^b IMEC   (Belgium)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^d UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Circuit analysis; Deep submicron; International technology roadmap for semiconductors (ITRS); Low noise design; Mixed analog digital integrated circuits (ICs); Substrate noise; Supply noise; Technology scaling

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTROMAGNETIC COUPLING; SCALABILITY; SWITCHING NETWORKS;

DEEP SUBMICRON; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS (ITRS); LOW-NOISE DESIGN; MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS (IC); SUBSTRATE NOISE; SUPPLY NOISE; TECHNOLOGY SCALING;

ACOUSTIC NOISE;

EID: 33947111409     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.856049     Document Type: Article

References (21)

1. S. Donnay and G. Gielen, Eds., Substrate Noise Coupling in Mixed-Signal ASICs. Norwell, MA: Kluwer, 2003.
2. D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-Stale Circuits, vol. 28, no. 4, pp. 420-430, Apr. 1993.
3. J. Briaire and K. S. Krisch, "Principles of substrate crosstalk generation in CMOS circuits," IEEE Trans. Computer-Aided Design Integr. Circuits, vol. 19, no. 6, pp. 645-653, Jun. 2000.
4. R. Senthinathan and J. L. Prince, "Simultaneous switching ground noise calculation for packaged CMOS devices," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1724-1728, Nov. 1991.
5. M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. Gielen, and H. De Man, "Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal IC's with synchronous digital circuits," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1383-1395, Nov. 2002.
6. M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical design guides for substrate noise reduction in CMOS digital circuits," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 539-549, Mar. 2001.
7. P. Larsson, "Power supply noise in future ICs: A crystal ball reading," in Pwc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 467-474.
8. X. Aragones, J. L. Gonzales, and A. Rubio, "Substrate coupling trends in future CMOS technologies," in Proc. 7th Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Sep. 1997, pp. 235-244.
9. ITRS (Int. Technology Roadmap for Semiconductors) 2004 Edition (2004). [Online]. Available: http://public.itrs.net
10. M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, "Impact of technology scaling on substrate noise generation mechanisms," in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 501-504.
11. S. Kristiansson, S. P. Kagganti, T. Ewert, F. Ingvarson, J. Olsson, and K. O. Jeppson, "Substrate resistance modeling for noise coupling analysis," in Proc. IEEE Int. Conf. on Microelectronic Test Structures, Mar. 2003, pp. 124-129.
12. Substrate Noise Analyst™ tool (2005). [Online]. Available: http://www.cadence.com
13. K. Sakui, S. S. Wong, and B. A. Wooley, "The effects of impact ionization on the operation of neighboring devices and circuits," IEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1603-1607, Sep. 1994.
14. BSIM3 Manual [Online]. Available: http://www-device.eecs.berkeley.edu/ ~bsim
15. S. M. Sze, Semiconductor Devices: Physics and Technology Second Edition. New York: Wiley, Sep. 2001.
16. M. Badaroglu, P. Wambacq, G. Van der Plas, L. Balasubramanian, K. Tiri, I. Verbauwhede, S. Donnay, G. Gielen, and H. De Man, "Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1119-1130, Jul. 2004.
17. M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, "Digital ground bounce reduction by supply current shaping and clock frequency modulation," IEEE Trans. Computer-Aided Design Integr. Circuits, vol. 24, no. 1, pp. 65-76, Jan. 2005.
18. G. Van der Plas, C. Soens, M. Badaroglu, P. Wambacq, and S. Donnay, "Modeling and experimental verification of substrate coupling and isolation techniques in mixed-signal IC's on a lightly-doped substrate," in Proc. of VLSI Circuits Symp., Jun. 2005.
19. P. T. M. van Zeijl, J. W. Eikenbrock, P. P. Vervoort, S. Setty, J. Tangenberg, G. Shipton, E. Kooistra, I. Keekstra, and D. Belot, "A Bluetooth radio in 0.18 μm CMOS," in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, vol. 448, Feb. 2002, pp. 86-87.
20. R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256-268, Oct. 1974.
21. J. R. Pfiester, J. D. Shott, and J. D. Meindl, "Performance limits of CMOS ULSI," IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. 253-263, Feb. 1985.