36-GHz, 16×6-Bit ROM in InP DHBT technology suitable for DDS application

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 2, 2007, Pages 451-456

  Manandhar, Sanjeev ^a,b   Turner, Steven Eugene ^a,b   Kotecki, David E ^a,b  

^a IEEE   (United States)

^b The University of Maine   (United States)

Author keywords

Accumulator; Bipolar ROM; Decoder; Heterojunction bipolar transistor (HBT); High speed integrated circuits; Indium phosphide (InP)

Indexed keywords

ACCUMULATORS; BIPOLAR ROM; DECODERS; HIGH-SPEED INTEGRATED CIRCUITS; INDIUM PHOSPHIDE (INP);

DECODING; DIGITAL TO ANALOG CONVERSION; ENERGY DISSIPATION; INDIUM COMPOUNDS; POWER SUPPLY CIRCUITS; ROM;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 33847765067     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.889361     Document Type: Article

References (16)

1. C. Chang, J. Wang, and C. Yang, "Low-power and high-speed ROM modules for ASIC applications," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1516-1523, Oct. 2001.
2. O. Takahashi, N. Aoki, J. Silberman, and S. Dhong, "A 1-GHz logic circuit family with sense amplifiers," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 616-622, May 1999.
3. K. R. Elliott, "Direct digital synthesis for enabling next generation RF systems," in CSIC Dig., Nov. 2005, pp. 125-128.
4. S. E. Turner and D. E. Kotecki, "Direct digital synthesizer with ROM-less architecture at 13-GHz clock frequency in InP DHBT technology," IEEE Microw. Wireless Compon. Lett., vol 16, no. 5, pp. 296-298, May 2006.
5. S. E. Turner and D. E. Kotecki, "Direct digital synthesizer with sine-weighted DAC at 32-GHz clock frequency in InP DHBT technology," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2284-2290, Oct. 2006.
6. S. E. Turner, R. B. Elder, D. S. Jansen, and D. E. Kotecki, "4-bit adderaccumulator at 41-GHz clock frequency in InP DHBT technology," IEEE Microw. Wireless Compon. Lett., vol. 15, no. 3, pp. 144-146, Mar. 2005.
7. C. Kwok, N. Sheng, P. Asbeck, G. Kent, and S. Chen, "Ultra-high speed HBT sine ROM for direct digital synthesis application," in Proc. Nat. Aerospace Electronics Conf. (NAECON'94), Dayton, OH, May 1994, vol. 1, pp. 461-467.
8. D. A. Sunderland, R. A. Strauch, S. S. Wharfield, H. T. Peterson, and C. R. Cole, "CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications," IEEE J. Solid-State Circuits, vol. 19, no. 4. pp. 497-506, Aug. 1984.
9. max over 300 GHz in a new manufacturable technology," IEEE Electron Device Lett., vol. 25, no. 8, pp. 520-522, Aug. 2004.
10. K. Kawarada, M. Suzuki, H. Mukai, K. Toyoda, and Y. Kondo, "A fast 7.5 ns access 1K-bit RAM for cache-memory systems," IEEE J. Solid-State Circuits, vol. SC-13, no. 5, pp. 656-663, Oct. 1978.
11. C. Chuang, D. D. Tang, G. P. Li, E. Hackbarth, and R. R. Boedeker, "A 1.0-ns 5-kbit ECL RAM," IEEE J. Solid-State Circuits, vol. 21, no. 5, pp. 670-674, Oct. 1986.
12. D. V. Essl, R. W. Mitterer, B. F. Rehn, and J. R. Domitrowich, "Automated design optimization of integrated switching circuits," IEEE J. Solid-State Circuits, vol. SC-9, no. 1, pp. 14-19, Feb. 1974.
13. J. C. Barrett, A. Bergh, T. Hornak, and J. E. Price, "Design considerations for a high-speed bipolar READ-ONLY memory," IEEE J. Solid-State Circuits, vol. SC-5, no. 5, pp. 196-202, Oct. 1970.
14. S. Padoan and A. Boni, "High speed, low voltage ROMs," in Proc. 2nd IEEE-CAS Region 8 Workshop Analog Mixed IC Design, Sep. 1997, pp. 18-21.
15. H. Miyanaga, S. Konaka, Y. Kobayashi, Y. Yamamoto, and T. Sakai, "A 0.85-ns 1-kbit ECL RAM," IEEE J. Solid-State Circuits, vol. SC-21, no. 4, pp. 501-504, Aug. 1986.
16. S. Manandhar, S. E. Turner, and D. E. Kotecki, "A 20-GHz and 46-GHz, 32×6-bit ROM for DDS application in InP DHBT technology," in Proc. 13th IEEE Int. Conf. Electronics, Circuits and Systems (ICECS 2006), Nice, France, Dec. 2006, pp. 1003-1007.