A 20-GHz and 46-GHz, 32×6-bit ROM for DDS application in InP DHBT technology

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn , Issue , 2006, Pages 1003-1006

  Manandhar, Sanjeev ^a   Turner, Steven E ^a   Kotecki, David E ^a  

^a The University of Maine   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; ROM; TECHNOLOGY;

CLOCK FREQUENCIES; DIRECT DIGITAL SYNTHESIZERS (DDS); INP DHBT; INP DOUBLE HETEROJUNCTION BIPOLAR TRANSISTOR (DHBT); INTERNATIONAL CONFERENCES; PHASE TO AMPLITUDE CONVERTER; POWER SUPPLIES; READ ONLY MEMORY (ROM);

DIGITAL CIRCUITS;

EID: 33847756719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379960     Document Type: Conference Paper

References (5)

1. C. Chang, J. Wang, and C. Yang, "Low-Power and High-Speed ROM modules for ASIC applications," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1516-1523, October 2001.
2. O. Takahashi, N. Aoki, J. Silberman, and S. Dhong, "A 1-GHz logic circuit family with sense amplifiers," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 616-622, May 1999.
3. S. Manandhar, S. E. Turner, and D. E. Kotecki, "36-GHz, 16×6-bit ROM in InP DHBT Technology suitable for DDS application," IEEE J. Solid-State Circuits, Accepted for Publication, 2006.
4. max over 300 GHz in a new manufacturable technology," IEEE Electron Device Letters, vol. 25, no. 8, pp. 520-522, August 2004.
5. R. E. Makon, M. Lang, R. Driad, K. Schneider, M. Ludwig, R. Aidam, R. Quay, M. Schlechtweb, and G. Weimann, "Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs," Electronics Letters, vol. 41, no. 11, pp. 644-646, May 2005.