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Volumn 17, Issue 2, 2007, Pages 242-247

Single reference frame multiple current macroblocks scheme for multiple reference frame motion estimation in H.264/AVC

Author keywords

ISO IEC 14496 10 AVC; ITU T Rec. H.264; JVT; Motion estimation; Multiple reference frame; VLSI architecture

Indexed keywords

DECISION FLOW; MULTIPLE REFERENCE FRAME; VLSI ARCHITECTURE;

EID: 33847738637     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2006.887130     Document Type: Article
Times cited : (16)

References (16)
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  • 7
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  • 8
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    • Hardwarearchitecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
    • Y.-W.Huang, T.-C.Wang, B.-Y. Hsieh, and L.-G. Chen, " Hardwarearchitecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264," in Proc. IEEE Int. Symp. Circuits Syst., 2003, pp. 796-799.
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  • 11
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    • A VLSI architecture for variable block size video motion estimation
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    • S. Y. Yap and J. V. McCanny, "A VLSI architecture for variable block size video motion estimation," IEEE Trans. Circuit Syst. II, vol. 51, no. 7, pp. 384-389, Jul. 2004.
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  • 12
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    • Variable block size motion estimation algorithm and its hardware architecture for H.264
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    • J.-H. Lee and N.-S. Lee, "Variable block size motion estimation algorithm and its hardware architecture for H.264," in Proc. IEEE Int. Symp. Circuits and Systems, May 2004, vol. 3, pp. 740-743.
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  • 13
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.