Electrostatic funneling for precise nanoparticle placement: A route to wafer-scale integration

Nano Letters

Volumn 7, Issue 2, 2007, Pages 439-445

  Ma, Liang Chieh ^a   Subramanian, Ramkumar ^a   Huang, Hong Wen ^a   Ray, Vishva ^a   Kim, Choong Un ^a   Koh, Seong Jin ^a  

^a University of Texas at Arlington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DLVO THEORY; ELECTROSTATIC FUNNELING; ELECTROSTATIC POTENTIAL ENERGY GRADIENT;

CMOS INTEGRATED CIRCUITS; ELECTRIC FIELD EFFECTS; ELECTRIC POTENTIAL; GOLD; WSI CIRCUITS;

NANOPARTICLES;

EID: 33847692036     PISSN: 15306984     EISSN: None     Source Type: Journal    
DOI: 10.1021/nl062727c     Document Type: Article

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66. Here, "wafer-scale" refers to the simultaneous fabrication of millions of devices on a single wafer.