Strain engineering to improve data retention time in nonvolatile memory

IEEE Transactions on Electron Devices

Volumn 54, Issue 2, 2007, Pages 362-365

  Arghavani, R ^a   Derhacobian, N ^b   Banthia, V ^a   Balseanu, M ^a   Ingle, N ^a   M'Saad, H ^a   Venkataraman, S ^a   Yieh, E ^a   Yuan, Z ^a   Xia, L Q ^a   Krivokapic, Z ^c   Aghoram, U ^e   MacWilliams, K ^a   Thompson, S E ^d  

^a APPLIED MATERIALS INC   (United States)

^b Adesto Technologies   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d UNIVERSITY OF FLORIDA   (United States)

^e NONE

Author keywords

Compressive stress; Data retention; Nonvolatile memory (NVM); Read current; Strain; Tensile stress

Indexed keywords

ACTIVATION ENERGY; COMPRESSIVE STRESS; DATA STORAGE EQUIPMENT; ELECTRON TRAPS; GATES (TRANSISTOR); STRAIN; TENSILE STRESS;

DATA RETENTION; NONVOLATILE MEMORY; READ CURRENT;

NONVOLATILE STORAGE;

EID: 33847627398     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.888827     Document Type: Article

References (12)

1. S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig., 2004, pp. 221-224.
2. H. S. Yang, R. Malik, et al., "Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing," in IEDM Tech. Dig., 2004, pp. 1075-1078.
3. 2 SRAM cell," in IEDM Tech. Dig., 2004, pp. 657-660.
4. R. Arghavani, Z. Yuan, N. Ingle, K.-B. Jung, M. Seamons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, and A. Mascarenhas, "Stress management in sub-90-nm transistor architecture," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1740-1744, Oct. 2004.
5. A. Hamada and E. Takeda, "Hot-electron trapping activation energy in PMOSFET's under mechanical stress," IEEE Electron Device Lett., vol. 15, no. 1, pp. 31-32, Jan. 1994.
6. Y. M. Park, J. S. Lee, M. Kim, M. K. Choi, T. K. Kim, J. I. Han, D. W. Kwon, W. K. Lee, Y. H. Song, and K. D. Suh, "The mechanical stress effects on data retention reliability of NOR Flash memory," in IEDM Tech. Dig., 2001, pp. 711-715.
7. S. T. Smith, "Flexures: Elements of Elastic Mechanisms," CRC Press.
8. A. Gehring and S. Selberherr, "Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices," IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 306-319, Sep. 2004.
9. A. Kolodny, S. Nieh, B. Eitan, and J. Shappir, "Analysis and modeling of floating gate EEPROM cells," IEEE Trans. Electron Devices, vol. ED-33, no. 6, pp. 835-844, Jun. 1986.
10. W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, "Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain," IEEE Electron Device Lett., vol. 26, no. 6, pp. 410-412, Jun. 2005.
11. X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, S. E. Thompson, et al., "Strain-induced changes in the gate tunneling currents in p-channel MOSFETs," IEEE Electron Device Lett., submitted for publication.
12. A. Al-Bayati, L. Washington, L.-Q. Xia, M. Balseanu, Z. Yuan, M. Kawaguchi, F. Nouri, and R. Arghavani, Stress-Tunable Films Enhance Transistor Speed, 26th ed. London, England: SEMICONDUCTOR FABTECH, 2005, pp. 84-88.