Gate workfunction engineering in bulk FinFETs for sub-50-nm DRAM cell transistors

IEEE Electron Device Letters

Volumn 28, Issue 2, 2007, Pages 148-150

  Park, Ki Heung ^a   Lee, Jong Ho ^a  

^a Kyungpook National University   (South Korea)

Author keywords

DRAM; Dual poly gate; FinFET; Gate induced drain leakage (GIDL); Workfunction

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DRAIN CURRENT; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC FIELDS; LEAKAGE CURRENTS;

DUAL POLY-GATE; GATE WORKFUNCTION ENGINEERING; GATE-INDUCED DRAIN LEAKAGE;

FIELD EFFECT TRANSISTORS;

EID: 33847352020     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.889235     Document Type: Article

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