Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 32-33

  Chung, Sung Woong ^a   Lee, Sang Don ^a   Jang, Se Aug ^a   Yoo, Min Soo ^a   Kim, Kwang Ok ^a   Chung, Chai O ^a   Cho, Sung Yoon ^a   Cho, Heung Jae ^a   Lee, Lae Hee ^a   Hwang, Sun Hwan ^a   Kim, Jin Soo ^a   Lee, Bong Hoon ^a   Yoon, Hyo Geun ^a   Park, Hyung Soon ^a   Baek, Seung Joo ^a   Cho, Yun Seok ^a   Kwak, Noh Jung ^a   Sohn, Hyun Chul ^a   Moon, Seung Chan ^a   Yoo, Kyung Dong ^a   Jeong, Jae Goan ^a   Kim, Jin Woong ^a   Hong, Sung Joo ^a   Park, Sung Wook ^a   more..

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DRY ETCHING; SCALABILITY; THRESHOLD VOLTAGE;

DRIVING CURRENTS; TRANSISTOR STRUCTURE;

TRANSISTORS;

EID: 41149147144     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2006.1705202     Document Type: Conference Paper

References (5)

1. J. Y. Kim, et. al., Symposium on VLSI Tech. Dig., pp. 11-12, 2003.
2. J. Y. Kim, et. al., Symposium on VLSI Tech. Dig., pp. 34-35, 2005.
3. Y.-S. Kim, et. al., IEDM, pp. 325-328, 2005.
4. C. H. Lee, et. al., Symposium on VLSI Tech. Dig., pp. 130-131, 2004.
5. S.-Y. Lee, et. al., Symposium on VLSI Tech. Dig., pp. 200-201, 2004.