Minimizing reflections and cross-talk in chip packages

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 1, Issue , 2005, Pages 43-48

  Ndip, Ivan ^a   John, Werner ^a   Reich, Herbert ^a  

^a FRAUNHOFER IZM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CROSSTALK; ELECTRIC POWER SYSTEM INTERCONNECTION; MICROPROCESSOR CHIPS; PRODUCT DESIGN;

POWER/GROUND INTERPLANE; REFLECTION MINIMIZATION; SUBSTRATE TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 33847267325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. st IEEE Electronic Components and Technology Conference, 29 May-1 June 2001, pp.1496-1501.
2. Wada H., Makihara C., Park C., "High frequency package design technology using S parameter synthesize method", In Proc IEEE Wireless Communications Conference, 11-13 Aug. 1997, pp.151-155.
3. th International Symposium on Microelectronics (IMAPS 2004), Long Beach, CA, U.S.A, November 16-20, 2004.
4. Ndip I., John W., Reichl H., "Effects of Discontinuities and Technological Fluctuations on the RF Performance of BGA Packages", In Proc 55th IEEE Electronics Components and Technology Conference (ECTC 2005), Lake Buena Vista, FL, U.S.A. May 31 - June 3, 2005, pp. 1769-1775.
5. th IEEE Electronics Packaging Technology Conference (EPTC 2004), Singapore, December 8-10, 2004, pp. 643-648.
6. Ndip I., John W., Reichl H., "Efficient RF/Microwave Modeling of Discontinuities in Chip Packages and Boards", In Proc 35th IEEE European Microwave Conference (European Microwave Week 2005), Paris, France, October 3-7, 2005.
7. Bogatin E., Signal Integrity - Simplified, Prentice Hall, 2004.
8. th IEEE Topical Meeting on Electronic Performance of Electronic Packaging, pp. 135-138, 1997.