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Volumn , Issue , 2005, Pages 2148-2151

Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE NUMBERS; CMOS PROCESS; COMPUTATIONAL MEMORY; FLOATING-GATE; FOWLER-NORDHEIM TUNNELING; LARGE ARRAYS; PREDICTIVE ALGORITHMS; PREDICTIVE METHODS;

EID: 33847153046     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465045     Document Type: Conference Paper
Times cited : (25)

References (7)
  • 1
    • 0031191573 scopus 로고    scopus 로고
    • Self learning analog neural network LSI with high-resolution nonvolatile analog memory and a partially serrial weight-update architecture
    • T. Morie, O. Fujita, and K. Uchimura, "Self learning analog neural network LSI with high-resolution nonvolatile analog memory and a partially serrial weight-update architecture," IEICE Trans. Electron, vol. E80-C, no. 7, pp. 990-995, 1997.
    • (1997) IEICE Trans. Electron , vol.E80-C , Issue.7 , pp. 990-995
    • Morie, T.1    Fujita, O.2    Uchimura, K.3
  • 5
    • 36849097956 scopus 로고
    • Fowlernordheim tunneling into thermally grown sio
    • M. Lenzlinger and E. Snow, "Fowlernordheim tunneling into thermally grown sio," Journal of Applied Physics, vol. 40, no. 6, pp. 278-283, 1969.
    • (1969) Journal of Applied Physics , vol.40 , Issue.6 , pp. 278-283
    • Lenzlinger, M.1    Snow, E.2
  • 6
    • 84886448075 scopus 로고    scopus 로고
    • Performance and reliability evaluations of p-channel flash memories with different programming schemes
    • S. Chung, S. Kuo, C. Yih, and T. Chao, "Performance and reliability evaluations of p-channel flash memories with different programming schemes," IEDM Tech. Dig., pp. 295-298, 1997.
    • (1997) IEDM Tech. Dig , pp. 295-298
    • Chung, S.1    Kuo, S.2    Yih, C.3    Chao, T.4
  • 7
    • 0035429465 scopus 로고    scopus 로고
    • A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution
    • May
    • S. Kinoshita, T. Morie, M. Nagata, and A. Iwata, "A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1286-1290, May 2003.
    • (2003) IEEE Journal of Solid-State Circuits , vol.36 , pp. 1286-1290
    • Kinoshita, S.1    Morie, T.2    Nagata, M.3    Iwata, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.