A fully programmable CMOS block matrix transform imager architecture

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 189-192

  Bandyopadhyay, Abhishek ^a   Hasler, Paul ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); IMAGING SYSTEMS; MICROPROCESSOR CHIPS;

FLOATING GATES; POWER CONSUMPTION; PROGRAMMABLE BLOCK MATRIX TRANSFORM IMAGER;

PROM;

EID: 0242527300     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. J. C. Gealow and C. G. Sodini, "A pixel-parallel image processor using logic pitch-matched to dynamic memory," IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 65-73, June 1999.
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6. R. C. Gonzales and R. E. Woods, Eds., Digital Image Processing. Delhi, India: Pearson Education Asia, 2002.
7. P. Hasler, A. Bandyopadhyay, and P. Smith, "A matrix transform imager allowing high fill factor," in Proceedings of the IEEE International Symposium on Circuits and Systems, Phoenix, AZ, May 2002.