Virtual design and qualification of IC backend structures

7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

Volumn 2006, Issue , 2006, Pages

  Van Silfhout, R B R ^a   Van Der Sluis, O ^a   Van Driel, W D ^b,c   Janssen, J H J ^b   Zhang, G Q ^b,c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CRACK INITIATION; FAILURE ANALYSIS; MATHEMATICAL MODELS; RELIABILITY; SELF ASSEMBLY;

INTEGRATED CIRCUIT (IC) WAFER BACKEND DEVELOPMENT; PACKAGE DEVELOPMENT; PROCESS DEVELOPERS; WAFERFAB PROCESSES;

INTEGRATED CIRCUITS;

EID: 33847125386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2006.1643962     Document Type: Conference Paper

References (8)

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2. W.D. van Driel, J.H.J. Janssen, R.B.R. van Silfhout, et al, "On Wire Failures in Micro Electronic Packages", EuroSimE2004, pp 53-57.
3. V. Fiori, S. Orain, "A Multi Scale Finite Element Methodology to Evaluate Wire Bond Pad Architectures", Proc. EuroSimE2005, pp 648-655.
4. Mercado, Lei L. et al., "Impact of Flip-Chip packaging on Copper/Low-k Structure," IEEE Trans. on Advanced Packaging, Vol. 26, No. 4 (2003), pp.433-440.
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6. Silfhout, R.B.R., Driel, W.D., Gils, M.A.J., et al, "Effect of Metal Layout Design on Passivation Crack Occurrence using both Experimental and Simulation Techniques", EuroSimE2004, pp 69-74.
7. W. van Driel, G.Q. Zhang, J.H.J. Janssen, L. J. Ernst, "Response Surface Modelling for Non-linear Packaging stresses", Journal of Electronic Packaging 125 (4), 2003, pp. 490-497.
8. Van Gils, M.A.J, Van der Sluis, O., Zhang, G.Q., Janssen, J.H.J., Voncken, R.M.J. "Analysis of Cu/low-k Bond Pad Delamination by using a Novel Failure Index", Proc. EuroSimE 2005, pp. 190-196.