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Volumn , Issue , 2004, Pages 53-57

On wire failures in micro-electronic packages

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAMINATION; ELECTRIC WIRE; ELECTRONICS PACKAGING; FAILURE (MECHANICAL); FINITE ELEMENT METHOD; INTERFACES (MATERIALS); OPTIMIZATION;

EID: 3843138371     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (20)

References (9)
  • 2
    • 3843131023 scopus 로고    scopus 로고
    • Reliability of wire bonding on low-k dielectric material in damascene copper integrated circuits PBGA assembly
    • M. Sivakumar, V. Kripesh, C.S. Choong, C.T. Chong, L.A. Lim, "Reliability of wire bonding on low-k dielectric material in damascene copper integrated circuits PBGA assembly", Microelectronics &Reliability 42, 2002, pp. 1535-1540.
    • (2002) Microelectronics & Reliability , vol.42 , pp. 1535-1540
    • Sivakumar, M.1    Kripesh, V.2    Choong, C.S.3    Chong, C.T.4    Lim, L.A.5
  • 4
  • 6
    • 3843145310 scopus 로고    scopus 로고
    • Wire loop development for advanced PBGA packages
    • W.K. Shu, "Wire loop development for advanced PBGA packages", IMAPS conference, 2002.
    • (2002) IMAPS Conference
    • Shu, W.K.1
  • 7
    • 0348197111 scopus 로고    scopus 로고
    • Packaging induced die stresses -effect of chip anisotropy and time-dependent behaviour of a moulding compound
    • W.D. van Driel, J.H.J. Janssen, G.Q. Zhang, D.G. Yang, L.J. Ernst, "Packaging Induced Die Stresses -Effect of Chip Anisotropy and Time-dependent Behaviour of a Moulding Compound", Journal of Electronic Packaging 125 (4), 2003, pp. 520-526.
    • (2003) Journal of Electronic Packaging , vol.125 , Issue.4 , pp. 520-526
    • Van Driel, W.D.1    Janssen, J.H.J.2    Zhang, G.Q.3    Yang, D.G.4    Ernst, L.J.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.