An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 31-34

  Shimazaki, Kenji ^a,b   Fukazawa, Mitsuya ^b   Nagata, Makoto ^b   Miyahara, Shingo ^a   Hirata, Masaaki ^a   Sato, Kazuhiro ^a   Tsujikawa, Hiroyuki ^a  

^a PANASONIC CORPORATION   (Japan)

^b KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; MICROPROCESSOR CHIPS; TIMING CIRCUITS;

BUILT IN NOISE PROBING; CHIP DELAY MONITORING; INTEGRATED TIMING; LARGE SCALE CIRCUITS;

SPURIOUS SIGNAL NOISE;

EID: 33847114467     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568600     Document Type: Conference Paper

References (5)

1. R. Saleh, "Clock Skew Verification in the Presence of IR-Drop in the Power Distribution Network," Trans. on CAD, VOL19, NO.6, Jun. 2000, pp. 635-644.
2. R. Ahmadi et al., "Timing Analysis in Presence of Power Supply and Ground Voltage Variations," in Proc. of ICCAD 2003, Nov. 2003, pp. 176-183
3. T. Okumoto et al.., "A Built-in Technique for Probing Power-Supply Noise Distribution within Large-Scale Digital Integrated Circuits," in Proc. of VLSI Circuits 2004, Jun. 2004, pp. 98-101.
4. S. Lin et al.., "Full-Chip Vectorless Dynamic Power Integrity Analysis and Verification Against 100uV/100ps-Resolution Measurement," in Proc. of CICC 2004, Oct. 2004, pp. 509-512.
5. M. Hashimoto et al., "Timing Analysis Considering Temporal Supply Voltage Fluctuation", in Proc. of ASP-DAC 2005, Jan. 2005, pp. 1098-1101.