Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 509-512

  Lin, Shen ^a   Nagata, Makoto ^b   Shimazaki, Kenji ^c   Satoh, Kazuhiro ^c   Sumita, Masaya ^c   Tsujikawa, Hiroyuki ^c   Yang, Andrew T ^a  

^a Apache Design Solutions   (United States)

^b KOBE UNIVERSITY   (Japan)

^c PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; EQUIVALENT CIRCUITS; MICROPROCESSOR CHIPS; RESONANCE; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

PARTIAL ELEMENT EQUIVALENT CIRCUIT (PEEC); POWER INTEGRATED ANALYSIS; SIMULTANEOUS SWITCHING OUTPUTS (SSO); STATIC TIME ANALYSIS (STA);

INTEGRATED CIRCUIT LAYOUT;

EID: 17044398147     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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