Fast identification of custom instructions for extensible processors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 2, 2007, Pages 359-368

  Chen, Xiaoyong ^b   Maskell, Douglas L ^a,b   Sun, Yang ^c  

^a IEEE   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Algorithm; Configurable processor; Instruction set extension (ISE)

Indexed keywords

CONFIGURABLE PROCESSORS; FAST ALGORITHMS; INSTRUCTION SET EXTENSION (ISE);

ALGORITHMS; CONSTRAINT THEORY; GRADIENT METHODS; GRAPH THEORY; INPUT OUTPUT PROGRAMS; PROBLEM SOLVING;

MICROPROCESSOR CHIPS;

EID: 33846572820     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.883915     Document Type: Conference Paper

References (18)

1. K. Atasu, L. Pozzi, and P. Tenne, "Automatic application-specific instruction-set extensions under microarchitectural constraints," in Proc. 40th Des. Autom. Conf., Jun. 2003, pp. 256-261.
2. L. Pozzi, K. Atasu, and P. Ienne, "Exact and approximate algorithms for the extension of embedded processor instruction sets," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 7, pp. 1209-1229, Jul. 2006.
3. P. Yu and T. Mitra, "Scalable custom instructions identification for instruction-set extensible processors," in Proc. Im. Conf. Compilers, Architectures, and Synth. Embed. Syst., Sep. 2004, pp. 69-78.
4. P. Biswas et al., "Introduction of local memory elements in instruction set extensions," in Proc. 41st Des. Autom. Conf., Jun. 2004, pp. 729-734.
5. P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, and P. Ienne, "1SEGEN: Generation of high-quality instruction set extensions by iterative improvement," in Proc. Des. Autom. and Test Eur. Conf., Mar. 2005, pp. 1246-1251.
6. N. Clark, H. Zhong, and S. A. Mahlke, "Processor acceleration through automated instruction set customization," in Proc. Annu. Int. Symp. Microarchit., Dec. 2003, pp. 129-140.
7. R. Razdan and M. D. Smith, "A high-performance microarchitecture with hardware-programmable functional units," in Proc. 27th Annu. Int. Symp. Microarchit., Nov. 1994, pp. 172-180.
8. B. Kastrup, A. Bink, and J. Hoogerbrugge, "ConCISe: A compiler-driven CPLD-based instruction set accelerator," in Proc. 7th IEEE Symp. Field-Programmable Custom Comput. Mach., Apr. 1999, pp. 92-101.
9. Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee, "CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit," in Proc, 27th Annu. Int. Symp. Comput. Architecture, Jun. 2000, pp. 225-235.
10. J. Cong et al., "Instruction set extension with shadow registers for configurable processors," in Proc. ACM 13th Int. Symp. Field-Programmable. Gate Arrays, Feb. 2005, pp. 99-106.
11. P. Ienne, L. Pozzi, and M. Vuletic, "On the limits of processor specialisation by mapping dataflow sections on ad-hoc functional units," Swiss Federal Inst. Technol. Lausanne, Comput. Sei. Dept., Lausanne, Switzerland, Tech. Rep. 01/376, Dec. 2001.
12. P. Yu and T. Mitra, "Characterizing embedded applications for instruction-set extensible processors," in Proc. 41st Des. Autom. Conf., Jun. 2004, pp. 723-728.
13. X. Chen and D. L. Maskell, "M2E: A multiple-input, multiple-output function extension for RISC-based extensible processors," in Proc. 19th Int. Conf. Architecture Comput. Syst., Mar. 2006, vol. 3894, pp. 191-201.
14. Altera Corp. Stratix III device handbook. [Online]. Available: http://www.altera.com/literature/hb/stx3/stratix3_handbook.pdf
15. Xilinx Inc. Virtex-4 user guide. [Online], Available: http://direct.xilinx.com/bvdocs/userguides/ug070.pdf
16. G. Kane and J. Heinrich, MIPS RISC Architecture. Englewood Cliffs, NJ: Prentice-Hall, 1992.
17. D. Goodwin and D. Petkov, "Automatic generation of application specific processors," in Proc. Int. Conf. Compilers, Architectures, and Synth. Embed. Syst., Nov. 2003, pp. 137-147.
18. M. R. Guthaus et al., "MiBench: A free, commercially representative embedded benchmark suite," in Proc. 4th IEEE Int. Workshop Workload Characterization, 2001, pp. 3-14.