Efficient array architectures for multi-dimensional lifting-based discrete wavelet transforms

Signal Processing

Volumn 87, Issue 5, 2007, Pages 1089-1099

  Xiong, Cheng yi ^a,b   Hou, Jian hua ^a,b   Tian, Jin wen ^b   Liu, Jian ^b  

^a SOUTH CENTRAL UNIVERSITY FOR NATIONALITIES   (China)

^b HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

Author keywords

Discrete wavelet transform; Lifting scheme; Multi dimensional; Parallel; VLSI architecture

Indexed keywords

BANDWIDTH; HARDWARE; IMAGE ANALYSIS; IMAGE SEGMENTATION; SIGNAL FILTERING AND PREDICTION; VLSI CIRCUITS;

CLOCK CYCLE; DISCRETE WAVELET TRANSFORM (DWT); VLSI ARCHITECTURE;

WAVELET TRANSFORMS;

EID: 33846570562     PISSN: 01651684     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sigpro.2006.10.001     Document Type: Article

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