A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 2, Issue , 2002, Pages 299-304

  Liu, Leibo ^a   Wang, Xuejin ^a   Meng, Hongying ^a   Zhang, Li ^a   Wang, Zhihua ^a   Chen, Hongyi ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Bandwidth; Computer architecture; Costs; Discrete wavelet transforms; Filters; Hardware; Image coding; MPEG 4 Standard; Transform coding; Very large scale integration

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COSTS; DIGITAL IMAGE STORAGE; FILTERS (FOR FLUIDS); HARDWARE; IMAGE CODING; MOTION PICTURE EXPERTS GROUP STANDARDS; VLSI CIRCUITS; WAVELET TRANSFORMS;

HARDWARE UTILIZATION; HIGH MEMORY BANDWIDTH; IMAGE COMPRESSION TECHNIQUES; MPEG-4 STANDARD; SPATIAL COMBINATIVE LIFTING ALGORITHMS; TRANSFORM CODING; VLSI ARCHITECTURES; VLSI IMPLEMENTATION;

DISCRETE WAVELET TRANSFORMS;

EID: 17444382562     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2002.1115240     Document Type: Conference Paper

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