HBD using cascode-voltage switch logic gates for SET tolerant digital designs

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2510-2515

  Casey, M C ^a,b   Bhuva, B L ^b   Black, J D ^a,c   Massengill, L W ^a,b  

^a IEEE   (United States)

^b VANDERBILT UNIVERSITY   (United States)

^c VANDERBILT UNIVERSITY   (United States)

Author keywords

Complementary metal oxide semiconductor (CMOS); Digital circuits; Logic design; Radiation hardening; Single event

Indexed keywords

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS); PULSE TERMINATION; SINGLE-EVENT; TRANSIENT PULSE;

DATA STORAGE EQUIPMENT; DIGITAL CIRCUITS; LOGIC DESIGN; RADIATION HARDENING;

CMOS INTEGRATED CIRCUITS;

EID: 33144460609     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.860715     Document Type: Conference Paper

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