Implications of characterization temperature on hardness assurance qualification

IEEE Transactions on Nuclear Science

Volumn 53, Issue 6, 2006, Pages 3132-3138

  Shaneyfelt, Marty R ^a,b   Schwank, James R ^a,b   Dodd, Paul E ^a,b   Hash, Gerald L ^b   Paillet, Philippe ^a,c   Felix, James A ^a,b   Baggio, Jacques ^a,c   Ferlet Cavrois, Veronique ^a,c  

^a IEEE   (United States)

^b SANDIA NATIONAL LABORATORIES   (United States)

^c CEA DIF   (France)

Author keywords

Hardness assurance testing; Integrated circuit radiation effects; Integrated circuit reliability; Radiation effects; Radiation hardening (electronics)

Indexed keywords

HARDNESS ASSURANCE TESTING; INTEGRATED CIRCUIT RADIATION EFFECTS; PARAMETRIC DEGRADATION;

ANNEALING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; OPTIMIZATION; RADIATION EFFECTS; STATIC RANDOM ACCESS STORAGE; THERMAL EFFECTS; TRANSISTORS;

HARDNESS;

EID: 33846317059     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.886009     Document Type: Conference Paper

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