A new hybrid fault detection technique for systems-on-a-chip

IEEE Transactions on Computers

Volumn 55, Issue 2, 2006, Pages 185-198

  Bernardi, Paolo ^a,b   Veiras Bolzani, Leticia Maria ^a,b   Rebaudengo, Maurizio ^a,b   Sonza Reorda, Matteo ^a,b   Vargas, Fabian Luis ^a,c   Violante, Massimo ^a,b  

^a IEEE   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Infrastructure IP; SoC dependability; Transient fault detection

Indexed keywords

INFRASTRUCTURE IP; PERFORMANCE OVERHEADS; SOC DEPENDABILITY; TRANSIENT FAULT DETECTION;

COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; SYSTEMS ANALYSIS;

FAULT TOLERANCE;

EID: 33846274695     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.15     Document Type: Article

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