On-line detection of control-flow errors in SoCs by means of an infrastructure IP core

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2005, Pages 50-58

  Bernardi, P ^b   Bolzani, L ^b   Rebaudengo, M ^b   Sonza Reorda, M ^b   Vargas, F ^a   Violante, M ^b  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL-FLOW ERRORS; INFRASTRUCTURE INTELLECTUAL PROPERTY (I-IP); ON-LINE DETECTION; SYSTEM-ON-CHIP (SOC);

COMPUTER SOFTWARE; ERROR ANALYSIS; INTEGRATION; INTELLECTUAL PROPERTY;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 27544505781     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2005.74     Document Type: Conference Paper

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