A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 6110-6113

  Chang, Hsiu Cheng ^a   Lin, Chien Chang ^a   Guo, Jiun In ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AVC/H.264; CLOCK CONSTRAINTS; CMOS TECHNOLOGY; CODEWORD; CONTEXT-BASED; DATA THROUGHPUT; H.264 VIDEO; HARDWARE COST; HIGH QUALITY VIDEO; LOOK UP TABLE; MAXIMUM SPEED; POWER CONSUMPTION; REALTIME PROCESSING; SYNTAX ELEMENTS; VARIABLE LENGTH CODES; VLSI ARCHITECTURES;

CMOS INTEGRATED CIRCUITS; COSTS; DATA COMPRESSION; DECODING; DESIGN; MOTION PICTURE EXPERTS GROUP STANDARDS; TABLE LOOKUP;

ARCHITECTURAL DESIGN;

EID: 33750119568     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1466034     Document Type: Conference Paper

References (13)

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