On metrics for comparing routability estimation methods for FPGAs

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 70-75

  Kannan, Parivallal ^a   Balachandran, Shankar ^a   Bhatia, Dinesh ^a  

^a The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; ESTIMATION; MATHEMATICAL MODELS; ROUTERS;

ROUTABILITY ESTIMATION METHODS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036054366     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513934.513937     Document Type: Conference Paper

References (11)

1. On routing demand and congestion estimation for FPGAs
2. VPR: A new packing, placement and routing tool for FPGA research
3. On routability prediction for field programmable gate arrays
4. RISA: Accurate and efficient placement routability modeling
5. fGREP - Fast generic routing demand estimation for placed FPGA circuits
6. Estimating routing congestion using probabilistic analysis
7. PathFinder: A negotiation-based performance-driven router for FPGAs
8. Interconnect complexity-aware FPGA placement using rent's rule
9. A stochastic model to predict the routability of field programmable gate arrays
10. Congestion estimation during top-down placement