An 8.1-ns column-access 1.6-Gb/s/pin DDR3 SDRAM with an 8:4 multiplexed data-transfer scheme

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 1, 2007, Pages 201-209

  Fujisawa, Hiroki ^a,b   Kubouchi, Shuichi ^b   Kuroki, Koji ^b   Nishioka, Naohisa ^b   Riho, Yoshiro ^b   Noda, Hiromasa ^a,b   Fujii, Isamu ^b   Yoko, Hideyuki ^b   Takishita, Ryuuji ^c   Ito, Takahiro ^c   Tanaka, Hitoshi ^a,c   Nakamura, Masayuki ^a,b  

^a IEEE   (Japan)

^b Elpida Memory Inc   (Japan)

^c HITACHI LTD   (Japan)

Author keywords

CMOS; Data transfer; DDR3; Double data rate (DDR); DRAM; Dual clock; Latency counter; Output buffer; SDRAM; ZQ calibration

Indexed keywords

DOUBLE DATA RATE (DDR); DUAL CLOCKS; LATENCY COUNTERS; OUTPUT BUFFERS; SDRAM; ZQ CALIBRATION;

CALIBRATION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DATA TRANSFER;

STATIC RANDOM ACCESS STORAGE;

EID: 33846194176     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.888298     Document Type: Article

References (8)

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