1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1-Gb SDR AM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 862-868

  Fujisawa, Hiroki ^a   Nakamura, Masayuki ^a   Takai, Yasuhiro ^a   Koshikawa, Yasuji ^a   Matano, Tatsuya ^a   Narui, Seiji ^a   Usuki, Narikazu ^a   Dono, Chiaki ^a   Miyatake, Shinichi ^b   Morino, Makoto ^b   Arai, Koji ^b   Kubouchi, Shuichi ^b   Fujii, Isamu ^b   Yoko, Hideyuki ^b   Adachi, Takao ^a  

^a Elpida Memory Inc   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Clock; Clock generation; CMOS; Double data rate (DDR); DRAM; Input latch; Output buffer; SDRAM

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); PERSONAL COMPUTERS; SERVERS;

CLOCK GENERATION; DOUBLE DATA RATE (DDR); INPUT LATCH; OUTPUT BUFFER; SDRAM;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 20844445960     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845555     Document Type: Conference Paper

References (11)

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