An 8.4ns column-access 1.3Gb/s/pin DDR3 SDRAM with an 8:4 multiplexed data-transfer scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Fujlsawa, Hiroki ^a   Kubouchi, Shuichi ^b   Kuroki, Kojl ^a   Nishioka, Naohisa ^a   Riho, Yoshiro ^a   Noda, Hiromasa ^a   Fujii, Isamu ^b   Yoko, Hideyuki ^b   Takishita, Ryuuji ^b   Ito, Takahiro ^b   Tanaka, Hitoshi ^b   Nakamura, Masayuki ^a  

^a Elpida Memory Inc   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS CONTROL; CMOS INTEGRATED CIRCUITS; DATA TRANSFER;

COLUMN ACCESS; DATA-TRANSFER SCHEME;

RANDOM ACCESS STORAGE;

EID: 33846231586     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. C. Park, et al., "A 512Mbit, 1.6Gbps/pin DDR3 SDRAM Prototype with Cio Minimization and Self-Calibration Techniques," Dig. Symp. VLSI Circuits, pp. 370-373, June, 2005.
2. H. Fujisawa, et al., "1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 Compatibly Designed 1-Gb SDRAM," IEEE J. Solid-State Circuits, vol. 40, pp. 862-869, Apr., 2005.
3. K. Saino, et al., "A Novel W/WNx/Dual-gate CMOS Technology for High-speed DRAM Having Enhanced Retention Time and Reliability," IEDM Dig. Tech. Papers, pp. 415-418, Dec., 2003.