A 16Mb MRAM featuring bootstrapped write drivers

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 454-457

  DeBrosse, J ^a   Arndt, C ^b   Barwin, C ^a   Bette, A ^b   Gogl, D ^b   Gow, E ^a   Hoenigschmid, H ^b   Lammers, S ^b   Lamorey, M ^a   Lu, Y ^c   Maffitt, T ^a   Maloney, K ^a   Obermeyer, W ^b   Sturm, A ^b   Viehmann, H ^b   Willmott, D ^a   Wood, M ^a   Gallagher, W J ^c   Mueller, G ^b   Sitaram, A R ^b  

^a IBM MICROELECTRONICS   (United States)

^b INFINEON TECHNOLOGIES   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

16Mb; 1T1MTJ; Architecture; Bootstrap and driver; Cell; Memory; MRAM

Indexed keywords

LEAKAGE CURRENTS; MAGNETIZATION; NETWORKS (CIRCUITS); OPTIMIZATION; PARAMETER ESTIMATION; REDUNDANCY; THRESHOLD VOLTAGE; TRANSISTORS;

16MB; 1T1MTJ; BOOTSTRAP; DRIVER; MAGNETIC RANDOM ACCESS MEMORY (MRAM); MEMORY;

RANDOM ACCESS STORAGE;

EID: 4544312036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A. Bette et al, "A high-speed 128Kbit MRAM core for future universal memory applications," Symposium on VLSI Circuits, p. 217, 2003.
2. M. Durlam et al, "A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects," Symposium on VLSI Circuits, p. 158, 2002.
3. A. Sitaram et al, "A 0.18μm logic-based MRAM technology for high performance nonvolatile memory applications," Symposium on VLSI Technology, p. 15, 2003.
4. M. Durlam et al, "A 0.18μm 4Mb toggling MRAM," IEDM, p. 995, 2003.
5. D. Worledge, "Magnetic phase diagram of two identical coupled nanomagnets," unpublished.