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Volumn 2006, Issue , 2006, Pages 1050-1059

Conformance of ECD wafer bumping to future demands on CSP, 3D integration, and MEMS

Author keywords

[No Author keywords available]

Indexed keywords

ALLOYS; ELECTROPLATING; LITHOGRAPHY; METALLIZING; MICROELECTROMECHANICAL DEVICES; PHOTOSENSITIVITY; THIN FILMS;

EID: 33845570883     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645783     Document Type: Conference Paper
Times cited : (13)

References (13)
  • 2
    • 0033687377 scopus 로고    scopus 로고
    • Wafer level chip scale packaging (WL-CSP): An overview
    • P. Garrou, "Wafer Level Chip Scale Packaging (WL-CSP): An Overview", IEEE Transactions on Advanced Packaging, Vol. 23, 2000
    • (2000) IEEE Transactions on Advanced Packaging , vol.23
    • Garrou, P.1
  • 8
    • 33845575217 scopus 로고    scopus 로고
    • Wafer-level hermetic cavity packaging
    • May
    • G. A. Riley, "Wafer-level Hermetic Cavity Packaging", Advanced Packaging, May 2005
    • (2005) Advanced Packaging
    • Riley, G.A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.