3D packaging issues for ultrasmall systems-in-a-cube

Solid State Technology

Volumn 48, Issue 4, 2005, Pages

  Snoeckx, Koen ^a   De Moor, Piet ^a,b   De Munck, Koen ^a,b   Beyne, Eric ^a,c  

^a IMEC   (Belgium)

^b Analog and RF Design Group   (France)

^c IMEC's Advanced Pack aging

Author keywords

[No Author keywords available]

Indexed keywords

ACCELEROMETERS; COST EFFECTIVENESS; DATA ACQUISITION; FLIP CHIP DEVICES; HEAT RADIATION; INTELLIGENT NETWORKS; LARGE SCALE SYSTEMS; MICROELECTROMECHANICAL DEVICES; REACTIVE ION ETCHING; SENSORS; SILICON; SOLAR ENERGY; SURFACE MOUNT TECHNOLOGY; THIN FILMS;

CHIP-SCALE PACKAGING (CSP); KNOWN GOOD DIE (KGD); SYSTEMS-IN-A-CUBE (SIC) ASSEMBLIES; WAFER-LEVEL PACKAGING TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 17444427642     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (4)

1. S. Stoukatch, et al, "High Density 3-D Stack Structure for SIP Solutions," 14th EMPC, Feb. 2003.
2. M. Reiche, "Ultrathin Wafers: Processing and Defect Issues," Proc. SPIE, Vol. 4600, pp. 80-87, 2001.
3. J.-J. Sun, et al., "High-aspect-ratio Copper Via Filling Used for Three-dimensional Chip Stacking," J. Electrochem. Soc., Vol. 150, No. 6, pp. G355-G358, 2003.
4. Oya, et al., "A Reliable and Compact Polymer-based Package for RF-MEMS Switches," IEDM, pp. 31-34, 2004.