-
3
-
-
0028055525
-
Predictability of load/store instruction latencies
-
Dec.
-
S. Abraham, R. Sugumar, B. R. Rau, and R. Gupta. Predictability of load/store instruction latencies. In Proceedings of the 26th Annual International Symposium on Microarchitecture, pages 139-152, Dec. 1993.
-
(1993)
Proceedings of the 26th Annual International Symposium on Microarchitecture
, pp. 139-152
-
-
Abraham, S.1
Sugumar, R.2
Rau, B.R.3
Gupta, R.4
-
10
-
-
12344327751
-
Long-range prefetching of delinquent loads
-
July
-
J. Collins, H. Wang, D. Tullsen, C. Hughes, Y. Lee, D. Lavery, and J. Shen. Long-range prefetching of delinquent loads. In Proceedings of 28th International Symposium on Computer Architecture, July 2001.
-
(2001)
Proceedings of 28th International Symposium on Computer Architecture
-
-
Collins, J.1
Wang, H.2
Tullsen, D.3
Hughes, C.4
Lee, Y.5
Lavery, D.6
Shen, J.7
-
11
-
-
84948988003
-
Deli: A new run-time control point
-
Nov.
-
G. Desoli, N. Mateev, E. Duesterwald, P. Faraboschi, and J. Fisher. Deli: A new run-time control point. In Proceedings of the 35th Annual International Symposium on Microarchitecture, Nov. 2002.
-
(2002)
Proceedings of the 35th Annual International Symposium on Microarchitecture
-
-
Desoli, G.1
Mateev, N.2
Duesterwald, E.3
Faraboschi, P.4
Fisher, J.5
-
12
-
-
4544322838
-
A cost-driven compilation framework for speculative parallelization of sequential programs
-
Z. Du, C. Lim, X. Li, C. Yang, Q. Zhao, and T. Ngai. A cost-driven compilation framework for speculative parallelization of sequential programs. In Proceedings of the ACM SIGPLAN conference on Programming Language Design and Implementation, pages 71-81, 2004.
-
(2004)
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 71-81
-
-
Du, Z.1
Lim, C.2
Li, X.3
Yang, C.4
Zhao, Q.5
Ngai, T.6
-
15
-
-
84976845370
-
Dynamic memory disambiguation using the memory conflict buffer
-
D. Gallagher, W. Chen, S. Mahlke, J. Gyllenhaal, and W. Hwu. Dynamic memory disambiguation using the memory conflict buffer. In Proceedings of the 6th International Conference on Architecture Support for Programming Languages and Operating Systems, pages 183-195, 1994.
-
(1994)
Proceedings of the 6th International Conference on Architecture Support for Programming Languages and Operating Systems
, pp. 183-195
-
-
Gallagher, D.1
Chen, W.2
Mahlke, S.3
Gyllenhaal, J.4
Hwu, W.5
-
16
-
-
0542399527
-
-
Technical Report Technical Report No. CSL-TR-95-673, Stanford University
-
M. Horowitz, M. Martonosi, T. Mowry, and M. Smith. Informing loads: Enabling software to observe and react to memory behavior. Technical Report Technical Report No. CSL-TR-95-673, Stanford University, 1995.
-
(1995)
Informing Loads: Enabling Software to Observe and React to Memory Behavior
-
-
Horowitz, M.1
Martonosi, M.2
Mowry, T.3
Smith, M.4
-
18
-
-
0027595384
-
The superblock: An effective technique for VLIW and superscalar compilation
-
Jan.
-
W. Hwu, S. Mahlke, W. Chen, P. Chang, N. Warter, R. Bringmann, R. Ouellette, R. Hank, T. Kiyohara, G. Haab, J. Holm, and D. Lavery. The superblock: An effective technique for VLIW and superscalar compilation. Journal of Supercomputing, Jan. 1993.
-
(1993)
Journal of Supercomputing
-
-
Hwu, W.1
Mahlke, S.2
Chen, W.3
Chang, P.4
Warter, N.5
Bringmann, R.6
Ouellette, R.7
Hank, R.8
Kiyohara, T.9
Haab, G.10
Holm, J.11
Lavery, D.12
-
19
-
-
0033075109
-
Prefetching using Markov predictors
-
Feb.
-
D. Joseph and D. Grunwald. Prefetching using Markov predictors. IEEE Transactions on Computers, 48(2): 121-133, Feb. 1999.
-
(1999)
IEEE Transactions on Computers
, vol.48
, Issue.2
, pp. 121-133
-
-
Joseph, D.1
Grunwald, D.2
-
21
-
-
3042569221
-
Physical experimentation with prefetching helper threads on Intel's Hyper-Threaded processors
-
Mar.
-
D. Kim, S. Liao, P. Wang, J. Cuvillo, X. Tian, X. Zou, H. Wang, D. Yeung, M. Gikar, and J. Shen. Physical experimentation with prefetching helper threads on Intel's Hyper-Threaded processors. In Proceedings of the Second Annual IEEE/ACM International Symposium on Code Generation and Optimization with Special Emphasis on Feedback-Directed and Runtime Optimization, Mar. 2004.
-
(2004)
Proceedings of the Second Annual IEEE/ACM International Symposium on Code Generation and Optimization with Special Emphasis on Feedback-directed and Runtime Optimization
-
-
Kim, D.1
Liao, S.2
Wang, P.3
Cuvillo, J.4
Tian, X.5
Zou, X.6
Wang, H.7
Yeung, D.8
Gikar, M.9
Shen, J.10
-
23
-
-
85008031236
-
MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research
-
A. KleinOsowski and D. Lilja. MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters, 1, 2002.
-
(2002)
Computer Architecture Letters
, pp. 1
-
-
Kleinosowski, A.1
Lilja, D.2
-
24
-
-
0036036248
-
Post-pass binary adaptation for software-based speculative precomputation
-
June
-
S. Liao, P. Wang, H. Wang, G. Hoflehner, D. Lavery, and J. Shen. Post-pass binary adaptation for software-based speculative precomputation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 117-128, June 2002.
-
(2002)
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 117-128
-
-
Liao, S.1
Wang, P.2
Wang, H.3
Hoflehner, G.4
Lavery, D.5
Shen, J.6
-
26
-
-
0027695220
-
Sentinel scheduling: A model for compiler-controlled speculative execution
-
Nov.
-
S. Mahlke, W. Chen, R. Bringmann, R.Hank, W. Hwu, B. R. Rau, and M. Schlansker. Sentinel scheduling: a model for compiler-controlled speculative execution. ACM Transactions on Computer Systems, 11(4), Nov. 1993.
-
(1993)
ACM Transactions on Computer Systems
, vol.11
, Issue.4
-
-
Mahlke, S.1
Chen, W.2
Bringmann, R.3
Hank, R.4
Hwu, W.5
Rau, B.R.6
Schlansker, M.7
-
27
-
-
0026980852
-
Effective compiler support for predicated execution using the hyperblock
-
Dec.
-
S. Mahlke, D. Lin, W. Chen, R. Hank, and R. Bringmann. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the 25th Annual International Symposium on Microarchitecture, pages 45-54, Dec. 1992.
-
(1992)
Proceedings of the 25th Annual International Symposium on Microarchitecture
, pp. 45-54
-
-
Mahlke, S.1
Lin, D.2
Chen, W.3
Hank, R.4
Bringmann, R.5
-
33
-
-
0009755242
-
-
Technical Report Technical Report HPL-94-115, HP Labs, Nov.
-
B. R. Rau. Iterative modulo scheduling. Technical Report Technical Report HPL-94-115, HP Labs, Nov. 1995.
-
(1995)
Iterative Modulo Scheduling
-
-
Rau, B.R.1
-
37
-
-
33847129885
-
An efficient hardware algorithm for exploiting multiple arithmetic units
-
Jan.
-
R. Tomasulo. An efficient hardware algorithm for exploiting multiple arithmetic units. IBM Journal, 44-5:25-33, Jan. 1967.
-
(1967)
IBM Journal
, vol.44
, Issue.5
, pp. 25-33
-
-
Tomasulo, R.1
|