Design of transport triggered architecture processors for wireless encryption

Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools

Volumn 2005, Issue , 2005, Pages 144-152

  Hämäläinen, Panu ^a   Heikkinen, Jari ^a   Hännikäinen, Marko ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; ENERGY UTILIZATION; LOCAL AREA NETWORKS; LOGIC GATES; PUBLIC KEY CRYPTOGRAPHY; WIRELESS TELECOMMUNICATION SYSTEMS;

CLOCK SPEED; ENCRYPTION ALGORITHMS; TRANSPORT TRIGGERED ARCHITECTURE (TTA) DESIGN; WIRELESS APPLICATION DOMAINS;

MICROPROCESSOR CHIPS;

EID: 33845318873     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2005.33     Document Type: Conference Paper

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